
4
LTC1409
POWER REQUIRE E TS
W U
(Note 5)
TI I G CHARACTERISTICS
W U
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
fSAMPLE(MAX)
Maximum Sampling Frequency
q
800
kHz
tCONV
Conversion Time
q
900
1250
ns
tACQ
Acquisition Time
q
150
ns
t1
CS to RD Setup Time
(Notes 9, 10)
q
0ns
t2
CS
↓ to CONVST↓ Setup Time
(Notes 9, 10)
q
10
ns
t3
NAP/SLP
↓ to SHDN↓Setup Time
(Notes 9, 10)
q
10
ns
t4
SHDN
↑ to CONVST↓ Wake-Up Time (Note 10)
200
ns
t5
CONVST Low Time
(Notes 10, 11)
q
50
ns
t6
CONVST to BUSY Delay
CL = 25pF
10
ns
q
60
ns
t7
Data Ready Before BUSY
↑
20
35
ns
q
15
ns
t8
Delay Between Conversions
(Note 10)
q
40
ns
t9
Wait Time RD
↓ After BUSY↑
q
–5
ns
t10
Data Access Time After RD
↓
CL = 25pF
15
35
ns
q
45
ns
CL = 100pF
20
45
ns
q
60
ns
t11
Bus Relinquish Time
830
ns
0
°C ≤ TA ≤ 70°C
q
35
ns
–40
°C ≤ TA ≤ 85°C
q
40
ns
t12
RD Low Time
q
t10
ns
t13
CONVST High Time
q
50
ns
t14
Aperture Delay of Sample-and-Hold
– 1.5
ns
Note 5: VDD = 5V, fSAMPLE = 800kHz, tr = tf = 5ns unless otherwise
specified.
Note 6: Linearity, offset and full-scale specifications apply for a single-
ended +AIN input with –AIN grounded.
Note 7: Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
Note 8: Bipolar offset is the offset voltage measured from – 0.5LSB when
the output code flickers between 0000 0000 0000 and 1111 1111 1111.
Note 9: Guaranteed by design, not subject to test.
Note 10: Recommended operating conditions.
The q indicates specifications which apply over the full operating
temperature range; all other limits and typicals TA = 25°C.
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: All voltage values are with respect to ground with DGND and
AGND wired together (unless otherwise noted).
Note 3: When these pin voltages are taken below VSS or above VDD, they
will be clamped by internal diodes. This product can handle input currents
greater than 100mA below VSS or above VDD without latch-up.
Note 4: When these pin voltages are taken below VSS they will be clamped
by internal diodes. This product can handle input currents greater than
100mA below VSS without latchup. These pins are not clamped to VDD.
(Note 5)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
ISS
Negative Supply Current
CS High
q
10
15
mA
Nap Mode
CONVST = CS = RD = SHDN = 0V, NAP/SLP = 5V
10
A
Sleep Mode
CONVST = CS = RD = SHDN = 0V, NAP/SLP = 0V
1
A
PDISS
Power Dissipation
q
80
120
mW
Nap Mode
CONVST = CS = RD = SHDN = 0V, NAP/SLP = 5V
3.8
6
mW
Sleep Mode
CONVST = CS = RD = SHDN = 0V, NAP/SLP = 0V
0.01
mW